? semiconductor components industries, llc, 2015 march, 2015 ? rev. p0 1 publication order number: esd7102/d esd7102, szesd7102 product preview esd protection diodes low capacitance esd protection diodes for high speed data line the esd7102 transient voltage suppressor is designed to protect high speed data lines from esd. ultra?low capacitance and low esd clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. the small form factor, flow?through style package allows for easy pcb layout and matched trace lengths necessary to maintain consistent impedance between high speed differential lines such as usb 3.0 and hdmi. features ? low capacitance (0.3 pf typical, i/o to gnd) ? short to battery survivability ? protection for the following iec standards: iec 61000?4?2 level 4 (esd) ? low esd clamping voltage (30 v typical, +16 a tlp, i/o to gnd) ? sz prefix for automotive and other applications requiring unique site and control change requirements; aec?q101 qualified and ppap capable ? these devices are pb?free and are rohs compliant typical applications ? usb2.0/3.0 ? lvds ? hdmi ? high speed differential pairs maximum ratings (t j = 25 c unless otherwise noted) rating symbol value unit operating junction temperature range t j ?55 to +125 c storage temperature range t stg ?55 to +150 c lead solder temperature ? maximum (10 seconds) t l 260 c iec 61000?4?2 contact iec 61000?4?2 air esd 8 15 kv kv stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. marking diagram sc?75 case 463 pin configuration and schematic www. onsemi.com pin 1 pin 2 pin 3 see detailed ordering, marking and shipping information in the package dimensions section on page 5 of this data sheet. ordering information = 1 2 3 xx m xx = specific device code m = date code 1
esd7102, szesd7102 www. onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise specified) parameter symbol conditions min typ max unit reverse working voltage v rwm i/o pin to gnd 5 16 v breakdown voltage v br i t = 1 ma, i/o pin to gnd 16.5 v reverse leakage current i r v rwm = 5 v, i/o pin to gnd 1 a clamping voltage (note 1) v c iec61000?4?2, 8 kv contact see figures 3 and 4 clamping voltage tlp (note 2) v c i pp = 8 a i pp = 16 a i pp = ?8 a i pp = ?16 a 25 30 ?5.5 ?10.8 v junction capacitance match c j v r = 0 v, f = 1 mhz between i/o1 to gnd and i/o 2 to gnd 5 10 % junction capacitance c j v r = 0 v, f = 1 mhz between i/o pins 0.2 0.4 pf junction capacitance c j v r = 0 v, f = 1 mhz between i/o pins and gnd 0.3 0.5 pf 3db bandwidth f bw r l = 50 5 ghz 1. for test procedure see figures 5 and 6 and application note and8307/d. 2. ansi/esd stm5.5.1 ? electrostatic discharge sensitivity testing using transmission line pulse (tlp) model. tlp conditions: z 0 = 50 , t p = 100 ns, t r = 4 ns, averaging window; t 1 = 30 ns to t 2 = 60 ns. 1.0 figure 1. typical iv characteristic curve figure 2. typical cv characteristic curve 0 1e?02 voltage (v) vbias (v) current (a) capacitance (pf) 2 1e?03 1e?04 1e?05 1e?06 1e?07 1e?08 1e?09 1e?10 1e?11 1e?12 1e?13 468101214 24 22 20 18 16 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 figure 3. iec61000?4?2 +8 kv contact esd clamping voltage ?50 150 time (ns) voltage (v) 0 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 ?10 50 100 150 200 400 250 300 350 figure 4. iec61000?4?2 ?8 kv contact esd clamping voltage ?20 10 time (ns) voltage (v) 0 20 40 80 120 20 0 140 160 180 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 100 60 02468101214 tbd tbd
esd7102, szesd7102 www. onsemi.com 3 iec 61000?4?2 spec. level test volt- age (kv) first peak current (a) current at 30 ns (a) current at 60 ns (a) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 i peak 90% 10% iec61000?4?2 w aveform 100% i @ 30 ns i @ 60 ns t p = 0.7 ns to 1 ns figure 5. iec61000?4?2 spec figure 6. diagram of esd clamping voltage test setup 50 50 cable tvs oscilloscope esd gun the following is taken from application note and8308/d ? interpretation of datasheet parameters for esd devices. esd voltage clamping for sensitive circuit elements it is important to limit the voltage that an ic will be exposed to during an esd event to as low a voltage as possible. the esd clamping voltage is the voltage drop across the esd protection diode during an esd event per the iec61000?4?2 waveform. since the iec61000?4?2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. on semiconductor has developed a way to examine the entire voltage waveform across the esd protection diode over the time domain of an esd pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all esd protection diodes. for more information on how on semiconductor creates these screenshots and how to interpret them please refer to and8307/d.
esd7102, szesd7102 www. onsemi.com 4 figure 7. positive tlp iv curve figure 8. negative tlp iv curve current (a) voltage (v) 18 040 35 30 51015 25 20 current (a) voltage (v) 0 ?14 ?2 ?4 ?6 ?8 ?12 ?10 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 note: tlp parameter: z 0 = 50 , t p = 100 ns, t r = 300 ps, averaging window: t 1 = 30 ns to t 2 = 60 ns. 16 14 12 10 8 6 4 2 0 tbd tbd transmission line pulse (tlp) measurement transmission line pulse (tlp) provides current versus voltage (i?v) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. a simplified schematic of a typical tlp system is shown in figure 9. tlp i?v curves of esd protection devices accurately demonstrate the product?s esd capability because the 10s of amps current levels and under 100 ns time scale match those of an esd event. this is illustrated in figure 10 where an 8 kv iec 61000?4?2 current waveform is compared with tlp current pulses at 8 a and 16 a. a tlp i?v curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. figure 9. simplified schematic of a typical tlp system dut l s oscilloscope attenuator 10 m v c v m i m 50 coax cable 50 coax cable figure 10. comparison between 8 kv iec 61000?4?2 and 8 a and 16 a tlp waveforms
esd7102, szesd7102 www. onsemi.com 5 with esd7102 without esd7102 figure 11. usb3.0 eye diagram with and without esd7102 at 5 gb/s figure 12. typical insertion loss 1 0.5 0 ?0.5 ?1 ?1.5 ?2 ?2.5 ?3 ?3.5 ?4 1.e+06 1.e+07 1.e+08 1.e+09 frequency (hz) s21 (db) ordering information device package shipping ? esd7102bt1g sc?75 (pb?free) 3000 / tape & reel SZESD7102BT1G* sc?75 (pb?free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *sz prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable.
esd7102, szesd7102 www. onsemi.com 6 package dimensions sc?75/sot?416 case 463?01 issue f notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. m 0.20 (0.008) d ?e? ?d? b e 3 pl 0.20 (0.008) e c l a a1 3 2 1 h e dim min nom max millimeters a 0.70 0.80 0.90 a1 0.00 0.05 0.10 b c 0.10 0.15 0.25 d 1.55 1.60 1.65 e e 1.00 bsc 0.027 0.031 0.035 0.000 0.002 0.004 0.004 0.006 0.010 0.059 0.063 0.067 0.04 bsc min nom max inches 0.15 0.20 0.30 0.006 0.008 0.012 h e l 0.10 0.15 0.20 1.50 1.60 1.70 0.004 0.006 0.008 0.061 0.063 0.065 0.70 0.80 0.90 0.027 0.031 0.035 0.787 0.031 0.508 0.020 1.000 0.039 mm inches scale 10:1 0.356 0.014 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 1.803 0.071 on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 esd7102/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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